Digital Fundamentals 11th 11E Thomas Floyd – Test Bank

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Exam
Name___________________________________
TRUE/FALSE. Write ‘T’ if the statement is true and ‘F’ if the statement is false.
1) The NAND gate is an example of combinational logic. 1) _______
2) This circuit is an example of the implementation of AND-OR-INVERT logic. 2) _______
3) The commonly accepted abbreviation for an exclusive-OR gate is XOR. 3) _______
4) X = ABC + BCD is in the form of a sum-of-products expression. 4) _______
5) The Karnaugh map below represents the expression, X = ACD + AB(CD + BC). 5) _______
6) NAND gates cannot be used to construct NOR gates. 6) _______
7) NOR gates can be used to construct AND gates. 7) _______
8) AB = A + B 8) _______
9) The effect of an inverted output being connected to the inverting input of another gate is to
effectively eliminate one of the inversions, resulting in a single inversion.
9) _______
10) The waveforms are correct for the logic circuit shown. 10) ______
MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
11) The reason that NOR logic networks are often drawn as shown in this figure, is ________.
11) ___
___
A) to help make the transition to a K-map
B) that it shows the actual gate arrangement
C) to minimize the number of parts required
D) to make it easier to determine the logical output
12) Which figure below represents AND-OR logic? 12) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
Figure 5-1
13) Which of the following logic expressions represents the logic diagram in Figure 5-1? 13) ______
A) X = AB + A B B) X = AB + AB C) X = A B + AB D) X = AB + AB
14) What type of logic circuit is represented by Figure 5-1? 14) ______
A) XNOR B) XAND C) XNAND D) XOR
Figure 5-2
15) A correct logic expression for Figure 5-2 is ________. 15) ______
A) X = ABC + ACD B) X = (AB)(ACCD)
C) X = ABC(CBD) D) X = (AB)(AC + CD)
16) How many gates, including inverters, are required to implement the equation,
as it is written?
16) ______
A) 1 B) 2 C) 3 D) 4
17) How many gates, including inverters, are required to implement the equation,
after it is simplified using Boolean algebra?
17) ______
A) 1 B) 2 C) 3 D) 4
18) The NAND gate is referred to as a “universal” gate, because it ________. 18) ______
A) is used in all the countries of the world
B) can be used to build all the other types of gates
C) can be found in almost all digital circuits
D) was the first gate to be integrated
Figure 5-3
19) Which circuit in Figure 5-3 represents the NAND implementation of a NOR gate? 19) ______
A) Figure (A). B) Figure( B). C) Figure (C). D) Figure (D).
20) Which circuit in Figure 5-3 represents the NAND implementation of an AND-OR function? 20) ______
A) Figure (A). B) Figure (B). C) Figure (C). D) Figure (D).
21) Which circuit in Figure 5-3 represents the NAND implementation of an inverter? 21) ______
A) Figure (A). B) Figure (B). C) Figure (C). D) Figure (D).
22) The relationship between a NAND gate and a negative-OR gate is expressed by ________. 22) ______
A) AB = A + B B) AB = + C) AB = A + B D) A + B = A + B
23) Which circuit is the logical equivalent of the Reference Circuit? 23) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
24) When the inverted output of one gate is connected to the inverted input of another gate,
________.
24) ______
A) the inversions cancel
B) one inversion cancels the other and only a single inversion results
C) a double inversion occurs and the signal is inverted
D) all of the above are correct
25) Why are multiple NAND gates often used in place of other single function gates? 25) ______
A) It makes it possible to use spare portions of NAND IC packages to implement other logic
functions, perhaps reducing the total IC package count.
B) NAND gates are cheaper than any other type of gate.
C) NAND gates are packaged more densely on IC’s than other types of gates.
D) It is easier to design logic circuits with a single gate type, since you only have to fully
understand how one type of gate works.
26) Which of the figures is the correct NAND logic implementation of the expression, X = ABC + DE? 26) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
27) The relationship between a NOR gate and a negative-AND gate is expressed by________. 27) ______
A) A + B = A + B B) AB = A + B C) AB = + D) A + B = A B
Figure 5-4
28) Which circuit in Figure 5-4 represents the NOR implementation of an OR gate? 28) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
29) Which circuit in Figure 5-4 represents the NOR implementation of an AND gate? 29) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
30) Which circuit in Figure 5-4 represents the NOR implementation of an inverter? 30) ______
A) Figure (A) B) Figure (B) C) Figure (C) D) Figure (D)
31) Which output waveform is correct for the circuit input waveforms shown?
31) ___
___
A) Output (A) B) Output (B) C) Output (C) D) Output (D)
32) The point identified as ‘X’ in this figure is referred to as ________. 32) ______
A) a reference point B) a tie point
C) common D) a node
33) What is the indication of an open in the output of a driving gate? 33) ______
A) The affected node will be stuck in the LOW state.
B) There is a signal loss to all load gates.
C) The affected node will be stuck in the HIGH state.
D) Only the output of the defective gate is affected.
34) What is the indication of a short to ground in the output of a driving gate? 34) ______
A) Only the output of the defective gate is affected.
B) The node is stuck in the LOW state.
C) The affected node will be stuck in the HIGH state.
D) There is a signal loss to all load gates.
35) What is the indication of a short on the input of a load gate? 35) ______
A) Only the output of the defective gate is affected.
B) There is a signal loss to all gates on the node.
C) The affected node will be stuck in the LOW state.
D) Both B and C are correct.
Figure 5-5
36) Based on the indications of probe A in Figure 5-5, what, if anything, is wrong with the circuit? 36) ______
A) The output appears to be shorted to Vcc, but is being pulsed by the pulser.
B) The output appears to be LOW, but is being pulsed by the pulser.
C) The logic probe is unable to determine the state of the circuit at that point and is blinking to
alert the technician to the problem.
D) Nothing appears to be wrong at that point.
37) Based on the indications of probe C in Figure 5-5, what, if anything, is wrong with the circuit? 37) ______
A) The gate being tested has not been connected to Vcc and ground.
B) The gate appears to be working correctly.
C) Pin 6 on the right-hand IC is shorted to ground.
D) Pin 5 on the right-hand IC appears to be open.
38) The output of a gate has an internal short. A current tracer will ________. 38) ______
A) identify the defective gate
B) be able to identify the defective load node
C) show whether the gate is shorted to Vcc or ground
D) probably not be able to locate the problem
39) An output gate is connected to four input gates; the circuit does not function. Preliminary tests
with a DMM indicate that power is applied; scope tests show that the primary input gate has a
pulsing signal, while the interconnecting node has no signal. The four load gates are all on
different IC’s. Which instrument will best help isolate the problem?
39) ______
A) Logic analyzer B) Current tracer C) Logic probe D) Oscilloscope
1) TRUE
2) FALSE
3) TRUE
4) TRUE
5) FALSE
6) FALSE
7) TRUE
8) TRUE
9) FALSE
10) FALSE
11) D
12) A
13) C
14) A
15) D
16) D
17) A
18) B
19) D
20) A
21) C
22) C
23) B
24) A
25) A
26) C
27) D
28) B
29) D
30) C
31) C
32) D
33) B
34) B
35) D
36) D
37) C
38) D
39) B

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